The semiconductor industry has been seeking more cost effective solutions for manufacturing integrated bipolar transistors and complementary metal oxide semiconductor (CMOS) devices (hereinafter Bi/CMOS) for mass applications of radio frequency (RF)/analog and wireless/fiber-based telecommunications for decades. Si/SiGe BiCMOS technology is widely used and has been quite successful. However, as CMOS adopts the thin silicon-on-insulator (SOI) substrate for lower power and higher speed (due to device scaling), the thick sub-collector of conventional bipolar junction transistors (BJTs) becomes incompatible with the integration of high-performance SOI CMOS devices.
In order to facilitate integration with SOI CMOS, lateral SOI BJTs have been proposed and studied. See, for example, S. Parke, et al. “A versatile, SOI CMOS technology with complementary lateral BJT's”, IEDM, 1992, Technical Digest, 13-16 Dec. 1992, page(s) 453-456; V. M. C. Chen, “A low thermal budget, fully self-aligned lateral BJT on thin film SOI substrate for lower power BiCMOS applications”, VLSI Technology, 1995. Digest of Technical Papers. 1995 Symposium on VLSI Technology, 6-8 Jun. 1995, page(s) 133-134; T. Shino, et al. “A 31 GHz fmax lateral BJT on SOI using self-aligned external base formation technology”, Electron Devices Meeting, 1998. IEDM '98 Technical Digest, International, 6-9 Dec. 1998, page(s) 953-956; T. Yamada, et al. “A novel high-performance lateral BJT on SOI with metal-backed single-silicon external base for low-power/low-cost RF applications”, Bipolar/BiCMOS Circuits and Technology Meeting, 1999. Proceedings of the 1999, 1999, page(s)129-132; and T. Shino, et al. “Analysis on High-Frequency Characteristics of SOI Lateral BJTs with Self-Aligned External Base for 2-GHz RF Applications”, IEEE, TED, vol. 49, No. 3, pp. 414, 2002.
Even though lateral SOI BJT devices are easier to integrate with SOI CMOS, the performance of such devices is quite limited. This is because the base width in the lateral SOI BJTs is determined by lithography. Hence it cannot be scaled down (less than 30 nm) readily without more advanced and more expensive lithography technologies such as e-beam lithography.
Another type of SOI BJT, which is a vertical SOI SiGe bipolar device with a fully depleted collector, has also been proposed, and demonstrated to offer higher base-collector breakdown voltage, higher early voltage and better breakdown voltage of the collector and emitter with an opened base (BVCEO)-cutoff frequency fT tradeoff. See, for example, U.S. Patent Application Publication 2002/0089038 A1 to T. Ning, and co-assigned U.S. application Ser. No. 10/328,694, filed Dec. 24, 2002. However, the integration process of these vertical SOI BJTs and SOI CMOS is still quite complex and expensive.
In view of the above, there is a need for providing a new and improved vertical SOI bipolar transistor that overcomes the drawbacks associated with prior art SOI BJTs.